Low-Latency Multi Rate SerDes PHY

 

Pin limitation is one of the greatest challenges in chip design. Therefore, high-speed SerDes technology is an essential requirement of today‘s high-performance ASICs.

EXTOLL‘s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Various digital control and tuning loops are employed to achieve robust performance across process and operating conditions. This allows a maximum of flexibility and also reduces the effort for migration to alternate target technologies. 

A single SerDes PHY block can consist of up to 8 bidirectional lanes and one common PLL that can be driven at various input reference clock frequencies to achieve line rates ranging from 2.5 to 25 Gbps. Multiple PHY blocks can be combined to construct wider links such as 16x PCIe. Higher line rates up to 28 Gbps can be supported on request.

 

Features

Operational features

• Support for line rates in the range of 2.5 up to 25 Gbps

• Compliant with PCIe up to Gen3

• PCIe Gen4 validation once PCIe 4.0 specification finalized

• 10G Ethernet (10GSFP+Cu defined in SFF-8431)

• Programmable transmitter with equalizer (4 tap FIR)

• Programmable RX linear equalizer (CTLE)

• Programmable RX DFE (5 tap)

• Digital Clock Data Recovery (CDR)

• Digital high speed PLL (low jitter)

Diagnostic features

• Pattern Generator (PRBS, user defined pattern) & Pattern Checker

• Concurrent Eye Monitor for equalization and channel analysis

• Far End and Near End Loopbacks

 

Physical features

• Available in TSMC 28nm HPC+ process

• Area of 1600 x 855 um per quad

• Designed for Flip-Chip

• Includes I/O pads & ESD structures

 

Deliverables

• Front- and backend integration views

• LIB, LEF, GDSII layout

• Fast Verilog simulation models

• Documentation

 

SerDes Diagram SerDes Eyediagram
Block Diagram Eye Diagram

 

Target Technologies

TSMC 28nm HPC+ process

(other processes on request)